From 885046b1c6290c8f71ea202d64ec0e7a37e7ee46 Mon Sep 17 00:00:00 2001 From: paullee0 Date: Fri, 10 Jan 2020 04:16:53 +0800 Subject: [PATCH] [DraftGeomUtils] OffsetWire() to accept input as Face as previously did. Forum Discussion - https://forum.freecadweb.org/viewtopic.php?f=23&t=42282&p=359233#p359233 --- src/Mod/Draft/DraftGeomUtils.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/Mod/Draft/DraftGeomUtils.py b/src/Mod/Draft/DraftGeomUtils.py index dbef8c3ba2..67865dd3a8 100644 --- a/src/Mod/Draft/DraftGeomUtils.py +++ b/src/Mod/Draft/DraftGeomUtils.py @@ -1218,8 +1218,9 @@ def offsetWire(wire,dvec,bind=False,occ=False,widthList=None, offsetMode=None, a 'dvec' vector to offset is now derived (and can be ignored) in this function if widthList and alignList are provided - 'dvec' to be obsolete in future ? ''' - # Accept 'wire' as a list of edges, use the list directly, or previously a wire - if isinstance(wire,Part.Wire): + # Accept 'wire' as a list of edges (use the list directly), or previously as a wire or a face (Draft Wire with MakeFace True or False supported) + + if isinstance(wire,Part.Wire) or isinstance(wire,Part.Face): edges = wire.Edges # Seems has repeatedly sortEdges, remark out here - edges = Part.__sortEdges__(wire.Edges) elif isinstance(wire, list): if isinstance(wire[0],Part.Edge): @@ -1273,7 +1274,7 @@ def offsetWire(wire,dvec,bind=False,occ=False,widthList=None, offsetMode=None, a firstDir = 1 firstAlign = 'Center' except: - print ("alignListC[0] has no value ") # Should no longer happen for ArchWall - as aligns are 'filled in' by ArchWall + pass # Should no longer happen for ArchWall - as aligns are 'filled in' by ArchWall # If not provided by alignListC checked above, check the direction of offset in dvec (not 'align')