[FEM] update Z88 tests

(I doubt that it is sensible to check if a hardcoded memory value is written. The test will fail if you use a non-default memory setting on your FreeCAD. The CI uses of course the default)
2022-03-25 19:04:21 +01:00
parent 7bc69a8cbb
commit b4befd14b3
4 changed files with 4 additions and 4 deletions
--- a/src/Mod/Fem/femtest/data/z88/ccx_cantilever_ele_hexa20/z88.dyn
+++ b/src/Mod/Fem/femtest/data/z88/ccx_cantilever_ele_hexa20/z88.dyn
@@ -23,7 +23,7 @@ Common entries for all modules         gemeinsame Daten fuer alle Module
 ---------------------------------------------------------------------------

  COMMON START
-    MAXGS    50000000
+    MAXGS  100000000
    MAXKOI   1200000
    MAXK       60000
    MAXE      300000
--- a/src/Mod/Fem/femtest/data/z88/ccx_cantilever_ele_tria6/z88.dyn
+++ b/src/Mod/Fem/femtest/data/z88/ccx_cantilever_ele_tria6/z88.dyn
@@ -23,7 +23,7 @@ Common entries for all modules         gemeinsame Daten fuer alle Module
 ---------------------------------------------------------------------------

  COMMON START
-    MAXGS    50000000
+    MAXGS  100000000
    MAXKOI   1200000
    MAXK       60000
    MAXE      300000
--- a/src/Mod/Fem/femtest/data/z88/ccx_cantilever_faceload/z88.dyn
+++ b/src/Mod/Fem/femtest/data/z88/ccx_cantilever_faceload/z88.dyn
@@ -23,7 +23,7 @@ Common entries for all modules         gemeinsame Daten fuer alle Module
 ---------------------------------------------------------------------------

  COMMON START
-    MAXGS    50000000
+    MAXGS  100000000
    MAXKOI   1200000
    MAXK       60000
    MAXE      300000
--- a/src/Mod/Fem/femtest/data/z88/ccx_cantilever_nodeload/z88.dyn
+++ b/src/Mod/Fem/femtest/data/z88/ccx_cantilever_nodeload/z88.dyn
@@ -23,7 +23,7 @@ Common entries for all modules         gemeinsame Daten fuer alle Module
 ---------------------------------------------------------------------------

  COMMON START
-    MAXGS    50000000
+    MAXGS  100000000
    MAXKOI   1200000
    MAXK       60000
    MAXE      300000